library verilog;
use verilog.vl_types.all;
entity present_sram_top is
    port(
        clk             : in     vl_logic;
        clk_uart        : in     vl_logic;
        start           : in     vl_logic;
        uart_txd        : out    vl_logic;
        result          : out    vl_logic_vector(63 downto 0)
    );
end present_sram_top;
